1. Field of the Invention
The invention relates to a circuit cell for test pattern generation and test pattern compression in integrated circuits with a built-in self-test function.
2. Description of the Related Art
U.S. Pat. No. 4,740,970 describes a circuit arrangement for use in an integrated circuit with built-in self-test logic. In order to extend possible operating modes of a BILBO (Built In Logic Block Observation) register cell, a multiplexer is provided which is driven by an additional control signal. Depending on the control signal, the multiplexer applies either a data input signal DI or a data output signal DO, which is buffer-stored, to an AND gate, the data output signal DO being fed back via a feedback line from a D flip-flop, which forms a data buffer store, to the multiplexer.
German Patent document DE 42 21 435 C2 describes an electronic module with a clock-controlled shift register test architecture. In the test device, an additional operating mode can be activated in which at least one sequence of a few register elements form a feedback shift register which is designed for generating a bit pattern sequence which has a width of n bits or for signature formation from a bit pattern sequence which has a width of n bits and is fed to the register elements on the module terminal side. In this case, a boundary scan cell is extended in such a way that it can be arranged for test pattern generation or for signature formation as a feedback shift register.
After fabrication, integrated circuits are subjected to a test method for testing their logical and dynamic behavior. This serves, on the one hand, to identify defective circuits and, on the other hand, to test the performance of the integrated circuits using the test results. In this case, the integrated circuits comprise multiple logic components which, for their part, comprise switching elements or transistors. Highly complex integrated circuits have multiple switching elements or transistors. In known test methods, stimulation test patterns are applied to the integrated circuits by an automatic test machine and response test patterns at the outputs of the integrated circuits are read out by the automatic test machine and compared with a desired test response. The test response pattern which is output by the circuit to be examined (the Device Under Test, or “DUT”) must correspond to the desired test response in order to identify that the integrated circuit is defect-free.
Integrated circuits are increasingly being constructed as BIST (Built-In Self-Test) structures with a built-in self test, i.e., logic comprising test pattern generators and test data evaluation modules are additionally implemented in the integrated circuit.
In order to facilitate test methods, these integrated circuits to be tested are increasingly being formed modularly from a multiplicity of circuit units that can be tested separately and are connected to one another via a data bus.
FIG. 1 schematically shows the construction of a known integrated circuit with a built-in self-test function which is constructed modularly from a multiplicity of circuit modules SM. Each circuit module SM comprises the actual logic circuit to be tested (DUT) and additionally comprises two BILBO registers, the first of the two BILBO registers being connected to the logic inputs of the logic circuit to be tested (DUT) and the other BILBO register being connected to the logic outputs of the logic circuit to be tested DUT.
The BILBO registers R shown in FIG. 1 are connected to one another in a serial test path. In the example shown in FIG. 1, a test data input signal TDI is applied to the register RiE, which is connected to the logic inputs of the logic circuit to be tested DUT of the circuit module i, and a test data output signal TDO is read out at the register RiA of the circuit module i. The registers RiE illustrated in FIG. 1, the register Ri+1,E, the register Ri+1,A, and the register RiA are interconnected via lines to form a serial test path. The BILBO registers R are registers that can independently generate test patterns and/or compress test pattern data. Conventional BILBO registers can be changed over between different operating states. In a first normal operating state, the BILBO register functions as a latch, in which the data present on the parallel data bus are applied to the logic circuit to be tested DUT or are read out from the logic circuit to be tested DUT via the data bus. In a second operating state, the BILBO register operates as a serial shift register for an initialization of reading test data out and in. In a further operating state, test patterns are generated in the BILBO register and transmitted. In a fourth operating state, processed test pattern data are received and compressed for test pattern evaluation.
BILBO registers R are in each case formed by a multiplicity of serially cascaded circuit cells. In this case, a test data input of one BILBO circuit cell is in each case connected to the test data output of a BILBO circuit cell connected upstream.
FIG. 2 shows a known BILBO circuit cell for the construction of a BILBO register R according to the prior art. The BILBO circuit cell shown in FIG. 2 has two control signal inputs (B1, B2), a clock signal input (CLK), a data input (DI) and a test data input (TDI). The control signals (B1, B2) are generated by a control circuit for setting the operating state of the BILBO register R. The data input DI is connected to one of the parallel data lines of the internal data bus of the integrated circuit. The test data input TDI is in each case connected to the test data output of the preceding BILBO circuit cell, a serial test data input signal being applied to the test data input of the first BILBO circuit cell for test purposes. The BILBO circuit cell according to the prior art as shown in FIG. 2 contains, on the one hand, a logic circuit constructed from logic gates and a flip-flop FF constructed from two latch circuits L1, L2. In this case, the logic circuit comprises a NOR gate, which logically NORs the second control signal B2 with the signal present at serial test data signal input TDI, an AND gate, which logically ANDs the data input signal present at the data input DT with the first control signal B1, the outputs of the NOR gate and of the AND gate in each case being applied to a signal input of an XNOR gate, which logically combines the logic output signal of the NOR gate and the logic output signal of the AND gate in an XNOR operation and applies the resulting signal to the input of the first latch L1 of the flip-flop FF. The two latch circuits L1, L2 of the flip-flop FF are clocked using the clock signal present at the clock signal input CLK, the second latch circuit L2 of the flip-flop receiving a clock signal which is inverted (by an inverter 1) relative to the clock signal present at the latch circuit L1.
FIG. 3 shows the internal construction of a known conventional latch circuit L according to the prior art in detail. The latch circuit L has a multiplexer MUX with two signal inputs and a signal output. At the first input of the multiplexer MUX, the latch circuit receives a data input signal, which is switched through to the output a of the multiplexer MUX in a manner clocked by the clock signal present at the clock signal input. The output a of the multiplexer is fed back via two inverters I1, I2 for holding the input signal to the second input e2 of the multiplexer MUX. The latch circuit L is clock-state-controlled, in which case, upon activation of the clock signal CLK, the bit present at the input e1 is transferred to the output a and, at the same time, is stored statically in the feedback loop.
The logic circuit which is illustrated in FIG. 2 and forms a part of the BILBO circuit cell according to the prior art and comprises the NOR gate, the AND gate and also the XNOR gate corresponds functionally to an XOR gate with a multiplexer. In this case, the multiplexer is connected into the data signal path between the data signal input D1 and the data output DO of the circuit cell shown in FIG. 2. On account of the logic gates connected in the data signal path, propagation time signal delays occur in the circuit cell for a BILBO register as illustrated in FIG. 2, which delays increase the switching time of the circuit cell. Consequently, the logic circuit which is shown in FIG. 2 and serves for coupling the test data into the data signal path leads to an undesirable reduction of the switching speed of the BILBO register. The test operation for testing the integrated circuits is delayed considerably on account of the reduced switching speed of the BILBO registers.